MAX19505–MAX19507/
MAX19515–MAX19517 Evaluation Kits
Output Bit Locations
Two drivers (U11 and U12) buffer the digital outputs of
the individual ADCs. These drivers are able to drive
large capacitive loads, which may be present at the
logic analyzer connection. The outputs of the buffers
are connected to J5. See Table 3 (10-bit ADCs) and
Table 4 (8-bit ADCs) for bit locations of header J5.
Serial Port Enable ( SPEN )
The SPEN pin selects the means of programming the
internal registers of the MAX19505 –MAX19507/
MAX19515–MAX19517 ADCs. SPEN is set high or low
based on the settings of jumper JU7, shown in Table 5.
When a shunt on JU7 is installed, the 3-wire serial port
is disabled and the part can be programmed through
jumpers JU1, JU2, and JU3 in parallel mode. When
JU7 is left open, SPEN is pulled to GND through R44.
Refer to the respective IC data sheet for more informa-
tion on SPEN and parallel programming. Note that
when the serial port is enabled, jumpers JU1, JU2, and
JU3 must be set to pins 1-3 for proper operation.
Table 3. Output Bit Locations (MAX19515,
MAX19516, MAX19517—10-Bit, Dual ADCs)
Shutdown (SHDN)
The MAX19505 –MAX19507/MAX19515 –MAX19517
ADCs can also be placed in a low-power shutdown
mode through jumper JU6. This pin has different effects
depending on the state of SPEN . When in SPI program-
ming mode, SHDN can select between two power-man-
agement states. When in parallel programming mode,
SHDN can enable/disable the IC.
When SPI programming is enabled ( SPEN = 0), the
SHDN pin is a toggle switch between two power-man-
agement states, shown in Figure 2 under the Power
Management group box of the software interface.
When a shunt is installed on JU6, SHDN is connected
to AVDD and the user can select the appropriate set-
tings for CHA Active , CHB Active , Standby , and A+B
Adder mode under the label **Use when SHDN = 1 (IC
pin 7)** . When no shunt is installed on JU6, SHDN is
connected to GND through R43 and the user can
select the appropriate settings for CHA Active , CHB
Active , Standby , and A+B Adder mode under the
label **Use when SHDN = 0 (IC pin 7)** .
Table 4. Output Bit Locations (MAX19505,
MAX19506, MAX19507—8-Bit, Dual ADCs)
SIGNAL
A
CHANNEL
B
DESCRIPTION
SIGNAL
A
CHANNEL
B
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
J5-44
J5-38
J5-36
J5-32
J5-30
J5-26
J5-24
J5-18
J5-16
J5-12
J5-110
J5-106
J5-104
J5-98
J5-96
J5-92
J5-90
J5-86
J5-84
J5-78
Data bit 0 (LSB)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Data bit 8
Data bit 9
D0
D1
D2
D3
D4
D5
D6
D7
DOR_
DCLK_
J5-36
J5-32
J5-30
J5-26
J5-24
J5-18
J5-16
J5-12
J5-10
J5-4
J5-104
J5-98
J5-96
J5-92
J5-90
J5-86
J5-84
J5-78
J5-112
J5-118
Data bit 0 (LSB)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Overrange bit
Clock bit
DOR_
DCLK_
J5-10
J5-4
J5-112
J5-118
Overrange bit
Clock bit
Note: See the EV kit schematic for all other nondata connections.
Note: See the EV kit schematic for all other nondata connections.
Table 5. Jumper JU7 Functions
SHUNT POSITION
Installed
Not installed*
*Default position.
SPEN PIN
Connected to AVDD
Connected to GND though a 100k ? pulldown resistor
3-WIRE SERIAL PORT
Disabled (parallel programming mode)
Enabled (SPI programming)
______________________________________________________________________________________
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